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MIT 6.004 Computation Structures, Spring 2017

by MIT OpenCourseWare · 172 videos

Total watch time

19h 17m

at 1× speed · exactly 19 hours, 17 minutes, 25 seconds at 1×

1×19h 17m 25s
1.25×15h 25m 56s
1.5×12h 51m 37s
1.75×11h 1m 23s
2×9h 38m 43s
Average video6m 44s
Longest33m 57s
Shortest1m 20s
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Videos (172)

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Videos to
Watched
1 1.2.1 What is Information? 2:16 2019-07-12
2 1.2.2 Quantifying Information 5:22 2019-07-12
3 1.2.3 Entropy 2:49 2019-07-12
4 1.2.4 Encoding 3:48 2019-07-12
5 1.2.5 Fixed-length Encodings 5:51 2019-07-12
6 1.2.6 Signed Integers: 2's complement 4:34 2019-07-12
7 1.2.7 Variable-length Encoding 3:40 2019-07-12
8 1.2.8 Huffman's Algorithm 2:09 2019-07-12
9 1.2.9 Huffman Code 1:20 2019-07-12
10 1.2.10 Error Detection and Correction 5:09 2019-07-12
11 1.2.11 Error Correction 1:34 2019-07-12
12 1.2.12 Worked Examples: Quantifying Information 2:09 2019-07-12
13 1.2.12 Worked Examples: Two's Complement Representation 5:49 2019-07-12
14 1.2.12 Worked Examples: Two's Complement Addition 4:58 2019-07-12
15 1.2.12 Worked Examples: Huffman Encoding 6:29 2019-07-12
16 1.2.12 Worked Examples: Error Correction 5:49 2019-07-12
17 2.2.1 Concrete Encoding of Information 4:15 2019-07-12
18 2.2.2 Analog Signaling 7:20 2019-07-12
19 2.2.3 Using Voltages Digitally 4:28 2019-07-12
20 2.2.4 Combinational Devices 6:06 2019-07-12
21 2.2.5 Dealing with Noise 4:20 2019-07-12
22 2.2.6 Voltage Transfer Characteristic 5:06 2019-07-12
23 2.2.7 VTC Example 2:18 2019-07-12
24 2.2.8 Worked Examples: The Static Discipline 5:40 2019-07-12
25 3.2.1 MOSFET: Physical View 8:00 2019-07-12
26 3.2.2 MOSFET: Electrical View 8:11 2019-07-12
27 3.2.3 CMOS Recipe 5:16 2019-07-12
28 3.2.4 Beyond Inverters 5:30 2019-07-12
29 3.2.5 CMOS Gates 3:41 2019-07-12
30 3.2.6 CMOS Timing 10:04 2019-07-12
31 3.2.7 Lenient Gates 4:22 2019-07-12
32 3.2.8 Worked Examples: CMOS Functions 1:47 2019-07-12
33 3.2.8 Worked Examples: CMOS Logic Gates 3:01 2019-07-12
34 4.2.1 Sum of Products 9:38 2019-07-12
35 4.2.2 Useful Logic Gates 5:56 2019-07-12
36 4.2.3 Inverting Logic 7:26 2019-07-12
37 4.2.4 Logic Simplification 5:00 2019-07-12
38 4.2.5 Karnaugh Maps 10:58 2019-07-12
39 4.2.6 Multiplexers 3:15 2019-08-12
40 4.2.7 Read-only Memories 5:39 2019-07-12
41 4.2.8 Worked Examples: Truth Tables 4:47 2019-07-12
42 4.2.8 Worked Examples: Gates and Boolean Logic 7:52 2019-07-12
43 4.2.8 Worked Examples: Combinational Logic Timing 1:42 2019-07-12
44 4.2.8 Worked Examples: Karnaugh Maps 3:39 2019-07-12
45 5.2.1 Digital State 10:05 2019-07-12
46 5.2.2 D Latch 6:12 2019-07-12
47 5.2.3 D Register 5:07 2019-07-12
48 5.2.4 D Register Timing 5:46 2019-07-12
49 5.2.5 Sequential Circuit Timing 6:52 2019-07-12
50 5.2.6 Timing Example 3:29 2019-07-12
51 5.2.7 Worked Example 1 2:38 2019-07-12
52 5.2.8 Worked Example 2 3:32 2019-07-12
53 6.2.1 Finite State Machines 5:56 2019-07-12
54 6.2.2 State Transition Diagrams 11:19 2019-07-12
55 6.2.3 FSM States 3:45 2019-07-12
56 6.2.4 Roboant Example 5:34 2019-07-12
57 6.2.5 Equivalent States; Implementation 6:04 2019-07-12
58 6.2.6 Synchronization and Metastability 9:52 2019-07-12
59 6.2.7 Worked Examples: FSM States and Transitions 6:18 2019-07-12
60 6.2.7 Worked Examples: FSM Implementation 3:31 2019-07-12
61 7.2.1 Latency and Throughput 6:17 2019-07-12
62 7.2.2 Pipelined Circuits 6:12 2019-07-12
63 7.2.3 Pipelining Methodology 6:00 2019-07-12
64 7.2.4 Circuit Interleaving 7:09 2019-07-12
65 7.2.5 Self-timed Circuits 6:22 2019-07-12
66 7.2.6 Control Structures 2:16 2019-07-12
67 7.2.7 Worked Examples: Pipelining 8:26 2019-07-12
68 7.2.7 Worked Examples: Pipelining 2 6:13 2019-07-12
69 8.2.1 Power Dissipation 11:49 2019-07-12
70 8.2.2 Carry-select Adders 5:41 2019-07-12
71 8.2.3 Carry-lookahead Adders 5:19 2019-07-12
72 8.2.4 Binary Multiplication 6:03 2019-07-12
73 8.2.5 Multiplier Tradeoffs 5:13 2019-07-12
74 8.2.6 Part 1 Wrap-up 3:03 2019-07-12
75 9.2.1 Datapaths and FSMs 5:18 2019-07-12
76 9.2.2 Programmable Datapaths 4:56 2019-07-12
77 9.2.3 The von Neumann Model 10:30 2019-07-12
78 9.2.4 Storage 6:38 2019-07-12
79 9.2.5 ALU Instructions 6:58 2019-07-12
80 9.2.6 Constant Operands 5:30 2019-07-12
81 9.2.7 Memory Access 2:57 2019-07-12
82 9.2.8 Branches 6:20 2019-07-12
83 9.2.9 Jumps 3:25 2019-07-12
84 9.2.10 Worked Examples: Programmable Architectures 9:02 2019-07-12
85 10.2.1 Intro to Assembly Language 8:13 2019-07-12
86 10.2.2 Symbols and Labels 4:25 2019-07-12
87 10.2.3 Instruction Macros 7:40 2019-07-12
88 10.2.4 Assembly Wrap-up 4:44 2019-07-12
89 10.2.5 Models of Computation 6:18 2019-07-12
90 10.2.6 Computability, Universality 6:22 2019-07-12
91 10.2.7 Uncomputable Functions 2:57 2019-07-12
92 10.2.8 Worked Examples: Beta Assembly 7:05 2019-07-12
93 11.2.1 Iterpretation and Compilation 9:36 2019-07-12
94 11.2.2 Compiling Expressions 8:34 2019-07-12
95 11.2.3 Compiling Statements 3:54 2019-07-12
96 11.2.4 Compiler Frontend 4:33 2019-07-12
97 11.2.5 Optimization and Code Generation 8:23 2019-07-12
98 11.2.6 Worked Examples 9:29 2019-07-12
99 12.2.1 Procedures 10:04 2019-07-12
100 12.2.2 Activation Records and Stacks 8:42 2019-07-12
101 12.2.3 Stack Frame Organization 5:49 2019-07-12
102 12.2.4 Compiling a Procedure 4:45 2019-07-12
103 12.2.5 Stack Detective 5:58 2019-07-12
104 12.2.6 Worked Examples: Procedures and Stacks 20:01 2019-07-12
105 13.2.1 Building Blocks 10:14 2019-07-12
106 13.2.2 ALU Instructions 7:01 2019-07-12
107 13.2.3 Load and Store 4:35 2019-07-12
108 13.2.4 Jumps and Branches 7:47 2019-07-12
109 13.2.5 Exceptions 6:05 2019-07-12
110 13.2.6 Summary 3:43 2019-07-12
111 13.2.7 Worked Examples: A Better Beta 9:40 2019-07-12
112 13.2.7 Worked Examples: Beta Control Signals 12:10 2019-07-12
113 14.2.1 Memory Technologies 4:17 2019-07-12
114 14.2.2 SRAM 6:59 2019-07-12
115 14.2.3 DRAM 5:11 2019-07-12
116 14.2.4 Non-volatile Storage; Using the Hierarchy 8:44 2019-07-12
117 14.2.5 The Locality Principle 7:13 2019-07-12
118 14.2.6 Caches 5:55 2019-07-12
119 14.2.7 Direct-mapped Caches 7:10 2019-07-12
120 14.2.8 Block Size; Cache Conflicts 6:05 2019-07-12
121 14.2.9 Associative Caches 9:33 2019-07-12
122 14.2.10 Write Strategies 4:42 2019-07-12
123 14.2.11 Worked Examples: Cache Benefits 14:20 2019-07-12
124 14.2.11 Worked Examples: Caches 13:11 2019-07-12
125 15.2.1 Improving Beta Performance 9:51 2019-07-12
126 15.2.2 Basic 5-Stage Pipeline 7:02 2019-07-12
127 15.2.3 Data Hazards 14:43 2019-07-12
128 15.2.4 Control Hazards 11:26 2019-07-12
129 15.2.5 Exceptions and Interrupts 5:19 2019-07-12
130 15.2.6 Pipelining Summary 1:56 2019-07-12
131 15.2.7 Worked Examples: Pipelined Beta 10:11 2019-07-12
132 15.2.7 Worked Examples: Beta Junkyard 8:17 2019-07-12
133 16.2.1 Even More Memory Hierarchy 7:10 2019-07-12
134 16.2.2 Basics of Virtual Memory 12:20 2019-07-12
135 16.2.3 Page Faults 6:48 2019-07-12
136 16.2.4 Building the MMU 10:17 2019-07-12
137 16.2.5 Contexts 4:58 2019-07-12
138 16.2.6 MMU Improvements 7:34 2019-07-12
139 16.2.7 Worked Examples: Virtual Memory 11:10 2019-07-12
140 17.2.1 Recap: Virtual Memory 4:58 2019-07-12
141 17.2.2 Processes 8:36 2019-07-12
142 17.2.3 Timesharing 10:26 2019-07-12
143 17.2.4 Handling Illegal Instructions 7:29 2019-07-12
144 17.2.5 Supevisor Calls 6:52 2019-07-12
145 17.2.6 Worked Examples: Operating Systems 7:16 2019-07-12
146 18.2.1 OS Device Handlers 6:08 2019-07-12
147 18.2.2 SVCs for Input/Output 8:53 2019-07-12
148 18.2.3 Example: Match Handler with OS 5:24 2019-07-12
149 18.2.4 Real Time 5:48 2019-07-12
150 18.2.5 Weak Priorities 5:11 2019-07-12
151 18.2.6 Strong Priorities 7:57 2019-07-12
152 18.2.7 Example: Priorities in Action! 6:53 2019-07-12
153 18.2.8 Worked Examples: Devices and Interrupts 6:43 2019-07-12
154 19.2.1 Interprocess Communication 9:01 2019-07-12
155 19.2.2 Semaphores 7:32 2019-07-12
156 19.2.3 Atomic Transactions 8:26 2019-07-12
157 19.2.4 Semaphore Implementation 4:17 2019-07-12
158 19.2.5 Deadlock 7:37 2019-07-12
159 19.2.6 Worked Examples: Semaphores 7:32 2019-07-12
160 20.2.1 System-level Interfaces 7:42 2019-07-12
161 20.2.2 Wires 9:43 2019-07-12
162 20.2.3 Buses 4:55 2019-07-12
163 20.2.4 Point-to-point Communication 6:47 2019-07-12
164 20.2.5 System-level Interconnect 3:57 2019-07-12
165 20.2.6 Communication Topologies 6:29 2019-07-12
166 21.2.1 Instruction-level Parallelism 13:58 2019-07-12
167 21.2.2 Data-level Parallelism 6:45 2019-07-12
168 21.2.3 Thread-level Parallelism 5:18 2019-07-12
169 21.2.4 Shared Memory & Caches 5:51 2019-07-12
170 21.2.5 Cache Coherence 9:31 2019-07-12
171 21.2.6 6.004 Wrap-up 5:44 2019-07-12
172 An Interview with Christopher Terman on Teaching Computation Structures 33:57 2019-07-12

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Watch time: 19h 17m · 172 videos

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