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Playlist · NPTEL IIT Delhi

Synthesis of Digital Systems

by NPTEL IIT Delhi · 26 videos

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1d 4h 3m

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1:14:18

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Videos (26)

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1 Outline - What is Synthesis? · Synthesis of Digital Systems - IITD 42:14 2018-01-19
2 Chip Design Flow and Hardware Modelling · Synthesis of Digital Systems - IITD 1:12:55 2018-01-19
3 VHDL: Introduction to Hardware Description Languages & VHDL Basics · Synthesis of Digital Systems - IITD 46:54 2018-01-24
4 VHDL: Modelling Timing - Events & Transactions · Synthesis of Digital Systems - IITD 57:32 2018-01-24
5 VHDL: Specifying Hardware Behaviour with Processes · Synthesis of Digital Systems - IITD 1:03:34 2018-02-04
6 VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries · Synthesis of Digital Systems - IITD 1:08:55 2018-02-04
7 Introduction to High-level Synthesis · Synthesis of Digital Systems - IITD 1:02:14 2018-02-11
8 Language front-end Design Representation · Synthesis of Digital Systems - IITD 1:09:05 2018-02-11
9 Compiler Transformation in High Level Synthesis: Constant Folding, · Synthesis of Digital Systems - IITD 1:10:49 2018-02-17
10 Memory Modelling & Compiler Transformation in High Level Synthesis · Synthesis of Digital Systems - IITD 1:02:20 2018-02-17
11 Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining · Synthesis of Digital Systems - IITD 1:07:21 2018-02-23
12 Hardware Transformations & ASAP / ALAP Scheduling · Synthesis of Digital Systems - IITD 1:02:44 2018-02-23
13 List Scheduling & Time-constrained Scheduling · Synthesis of Digital Systems - IITD 1:10:48 2018-03-01
14 Force Directed Scheduling & Register Allocation · Synthesis of Digital Systems - IITD 1:05:04 2018-03-01
15 High Level Synthesis and Timing Issues · Synthesis of Digital Systems - IITD 1:06:35 2018-03-01
16 Finite State Machine Synthesis: Introduction to FSM Encoding · Synthesis of Digital Systems - IITD 1:14:18 2018-03-09
17 Finite State Machine Synthesis: Identifying Common Cubes & Graph Embedding · Synthesis of Digital Systems - IITD 1:11:39 2018-03-17
18 The Retiming Problem · Synthesis of Digital Systems - IITD 1:06:57 2018-03-17
19 Efficient Solution to Retiming & Introduction to Logic Synthesis · Synthesis of Digital Systems - IITD 1:11:17 2018-03-24
20 Binary Decision Diagrams · Synthesis of Digital Systems - IITD 1:04:49 2018-03-24
21 Introduction to Logic Synthesis · Synthesis of Digital Systems - IITD 1:10:09 2018-04-01
22 Two-level Logic Optimisation · Synthesis of Digital Systems - IITD 1:09:44 2018-04-01
23 Multi-Level Logic Optimisation · Synthesis of Digital Systems - IITD 1:13:00 2018-04-01
24 Multi-level Logic Synthesis: Technology Mapping · Synthesis of Digital Systems - IITD 1:08:10 2018-04-08
25 Introduction to Timing Analysis · Synthesis of Digital Systems - IITD 1:12:07 2018-04-08
26 Timing Analysis & Critical Paths · Synthesis of Digital Systems - IITD 31:59 2018-04-08
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